diff -ruN u-boot-20060523/cpu/arm920t/start.S u-boot/cpu/arm920t/start.S
--- u-boot-20060523/cpu/arm920t/start.S 2006-09-25 17:04:03.000000000 +0800
+++ u-boot/cpu/arm920t/start.S 2006-10-22 17:51:13.000000000 +0800
@@ -140,10 +140,10 @@
ldr r0, =INTMSK
str r1, [r0]
# if defined(CONFIG_S3C2410)
- ldr r1, =0x3ff
+ ldr r1, =0x7ff
ldr r0, =INTSUBMSK
str r1, [r0]
-# endif
+# endif /*CONFIG_S3C2410*/
/* FCLK:HCLK
CLK = 1:2:4 */
/* default FCLK is 120 MHz ! */
@@ -220,6 +220,20 @@
/* END stuff after relocation */
#endif
+#ifdef CONFIG_S3C2410_NAND_BOOT
+ bl copy_myself
+
+ @ jump to ram
+ ldr r1, =on_the_ram
+ add pc, r1, #0
+ nop
+ nop
+1: b 1b @ infinite loop
+
+on_the_ram:
+#endif
+
+
ldr pc, _start_armboot
_start_armboot: .word start_armboot
@@ -236,6 +250,111 @@
*************************************************************************
*/
+#ifdef CONFIG_S3C2410_NAND_BOOT
+copy_myself:
+ mov r10, lr
+@ reset NAND
+ mov r1, #NAND_CTL_BASE
+ ldr r2, =0xf830 @ initial value
+ str r2, [r1, #oNFCONF]
+ ldr r2, [r1, #oNFCONF]
+ bic r2, r2, #0x800 @ enable chip
+ str r2, [r1, #oNFCONF]
+ mov r2, #0xff @ RESET command
+ strb r2, [r1, #oNFCMD]
+ mov r3, #0 @ wait
+
+1: add r3, r3, #0x1
+ cmp r3, #0xa
+ blt 1b
+2: ldr r2, [r1, #oNFSTAT] @ wait ready
+ tst r2, #0x1
+ beq 2b
+ ldr r2, [r1, #oNFCONF]
+ orr r2, r2, #0x800 @ disable chip
+ str r2, [r1, #oNFCONF]
+
+ @ get read to call C functions (for nand_read())
+ ldr sp, DW_STACK_START @ setup stack pointer
+ mov fp, #0 @ no previous frame, so fp=0
+
+ @ copy vivi to RAM
+ ldr r0, =UBOOT_RAM_BASE
+ mov r1, #0x0 @address
+ mov r2, #0x30000 @size
+ bl nand_read_ll
+
+ tst r0, #0x0
+ beq ok_nand_read
+
+#ifdef CONFIG_DEBUG_LL
+bad_nand_read:
